Are you a highly skilled and experienced engineer with a passion for low power design? Are you looking for an exciting opportunity to utilize your expertise in a dynamic and innovative environment? Look no further! We are seeking a Senior Low Power Engineer to join our team at Qualcomm. As a leader in the industry, Qualcomm offers a unique opportunity to work on cutting-edge technologies and play a key role in shaping the future of mobile devices. If you possess a strong background in low power design and have a proven track record of delivering successful projects, we want to hear from you!
Develop and implement low power design solutions for mobile devices.
Conduct research and stay updated on the latest low power design technologies and methodologies.
Collaborate with cross-functional teams to define project requirements and design specifications.
Lead and mentor junior engineers in low power design techniques.
Perform feasibility studies and provide recommendations for low power solutions.
Conduct rigorous testing and debugging to ensure high-quality and efficient low power designs.
Work closely with product teams to understand system-level power requirements and optimize designs accordingly.
Proactively identify potential issues and provide timely and effective solutions.
Participate in design reviews and provide valuable insights and suggestions.
Develop and maintain documentation for all low power design processes and procedures.
Prioritize and manage multiple projects simultaneously to meet strict deadlines.
Collaborate with external partners and vendors to integrate low power solutions into Qualcomm products.
Communicate project updates, issues, and solutions to management and stakeholders.
Adhere to industry standards and best practices for low power design.
Continuously improve and optimize low power design processes to increase efficiency and reduce costs.
Where is this job?
This job is located at Santa Clara, CA, USA
Job Qualifications
Bachelor’s Degree In Electrical Engineering Or Related Field. A Master’s Degree Is Preferred.
Minimum Of 5 Years Of Experience In Low Power Design At The Senior Level.
Strong Understanding Of Low Power Design Techniques, Including Power Gating, Clock Gating, And Voltage Scaling.
Proficiency In Industry-Standard Tools And Languages Such As Verilog, Systemverilog, And Synopsys Design Compiler.
Experience With Low Power Verification Methodologies, Such As Upf And Cpf, And Simulation Tools Such As Vcs And Questa.
Required Skills
System-Level Integration
Power Analysis
Circuit Design
Power Management
Thermal Management
Power Gating
Power Efficiency
Low Power Optimization
Energy Harvesting
Battery Life Extension
Sleep Modes
Soft Skills
Communication
Conflict Resolution
Customer Service
Leadership
Time Management
Creativity
Critical Thinking
Teamwork
Adaptability
Problem-Solving
